Double gated transistor

US6503784B1 · kind B1 · utility

Assignee

• Infineon Technologies Richmond, LP · US

Inventors

• Gerhard Enders · Glen Allen, US
• Thomas Schulz · Austin, US
• Dietrich Widmann · Unterhaching, DE
• Lothar Risch · Neubiberg, DE

Key dates

• Filing date: Sep 27, 2000
• Grant date: Jan 7, 2003
• Expiry date: Jan 28, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.