Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor
US6504191B2 · kind B2 · utility
4Cited by
12References
13Claims
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Key dates
| Filing date | Oct 8, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Oct 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.