DRAM cell configuration and fabrication method

US6504200B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Till Schlosser · Dresden, DE
• Bernhard Sell · Dresden, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Sep 12, 2001
• Grant date: Jan 7, 2003
• Expiry date: Sep 12, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.