MOSFET device having high-K dielectric layer
US6504214B1 · kind B1 · utility
83Cited by
11References
8Claims
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Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET device and method of fabrication. The MOSFET includes a gate having a gate electrode and a gate dielectric formed from a high-K material, the gate dielectric separating the gate electrode and a layer of semiconductor material. A source and a drain each formed by selective in-situ doped epitaxy and located adjacent opposite sides of the gate so as to define a body region from the layer of semiconductor material between the source and the drain and under the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.