Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through
US6506640B1 · kind B1 · utility
121Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.