Reliability test method and circuit for non-volatile memory
US6512710B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.