Method for forming single electron resistor memory
US6514820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 29, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/937
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method for forming a memory device that includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells formed from the method are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.