Field-effect-controlled transistor and method for fabricating the transistor
US6515319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/027
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.