Sub-cap and method of manufacture therefor in integrated circuit capping layers
US6515367B1 · kind B1 · utility
11Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2002 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Apr 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76888
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.