Dual layer hard mask for eDRAM gate etch process
US6518151B1 · kind B1 · utility
9Cited by
5References
17Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Aug 7, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.