MOSFET technology for programmable address decode and correction
US6521958B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology. An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. The MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2), such that the programmed MOSFET operates at reduced drain source current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.