Controlled gate length and gate profile semiconductor device and manufacturing method therefor
US6524916B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | May 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.