Integrated circuit configuration with at least one capacitor and method for producing the same

US6525363B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Josef Willer · Riemerling, DE
• Bernhard Sell · Dresden, DE
• Dirk Schumann · Lübbenau/Spreewald - Lubnjow/Błota, DE

Key dates

• Filing date: Oct 2, 2000
• Grant date: Feb 25, 2003
• Expiry date: Oct 5, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).