Patent · US Expired

Integrated memory with redundancy

US6525974B2 · kind B2 · utility

1Cited by

6References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ernst Neuhold · Angur Ada, AF
Heinz Honigschmid · Starnberg, DE
Georg Braun · Hersbruck, DE
Zoltan Manyoki · Gatineau, CA
Thomas Böhm · Zorneding, DE
Thomas Rohr · Aschheim, DE

Key dates

Filing date	Jun 22, 2001
Grant date	Feb 25, 2003
Priority date	—
Expiry date	Jun 22, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/846
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.