Liner materials
US6528180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | May 23, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/26
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.