MOSFET having a low aspect ratio between the gate and the source/drain

US6528855B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Qiuyi Ye · Hopewell Junction, US
• William R. Tonti · South Burlington, US
• Yujun Li · Poughkeepsie, US
• Jack A. Mandelman · Stormville, US

Key dates

• Filing date: Jul 24, 2001
• Grant date: Mar 4, 2003
• Expiry date: Jul 24, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.