Intermetal dielectric layer for integrated circuits
US6528886B2 · kind B2 · utility
1Cited by
11References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.