NAND array structure and method with buried layer
US6529410B1 · kind B1 · utility
49Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell during its programming. In one embodiment, the NAND array structure includes a buried layer at a junction between the substrate and a well in which the memory cells are formed. Programming is achieved using hot electron injection. In one embodiment, multiple memory cells are programmed simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.