Integrated memory having a row access controller for activating and deactivating row lines

US6532188B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stefan Dietrich · Potsdam, DE
• Thomas Hein · Hersbruck, DE
• Patrick Heyne · Hersbruck, DE
• Thilo Marx · Villingen-Schwenningen, DE
• Torsten Partsch · San Jose, US
• Sabine Kieser · Hausham, DE
• Peter Schroegmeier · Birkenfeld, DE
• Michael Sommer · Raubling, DE
• Christian Weis · Scheidegg, DE

Key dates

• Filing date: Oct 29, 2001
• Grant date: Mar 11, 2003
• Expiry date: Oct 29, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/18
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.