Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby
US6534869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1998 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.