Ferroelectric transistor and method for fabricating it
US6538273B2 · kind B2 · utility
4Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | May 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
Abstract
A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.