Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration

US6538913B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heinz Honigschmid · Starnberg, DE
• Thomas Rohr · Aschheim, DE

Key dates

• Filing date: Apr 4, 2001
• Grant date: Mar 25, 2003
• Expiry date: Aug 18, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/22
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The invention relates to a method for operating a ferroelectric memory configuration in the VDD/2 mode. The memory configuration has a large number of memory cells which each have at least one selection transistor, one storage capacitor with an upper and a lower electrode and one short-circuiting transistor whose source-drain junction is connected in parallel with the storage capacitor. After a read or write procedure in which the memory cells are driven via respectively associated word lines and via respectively associated bit lines which are precharged in a precharge phase, the short-circuiting transistor is driven during a standby phase and in the process short-circuits the electrodes in the storage capacitor. The method is characterized in that the time of the standby phase coincides with the time of the precharge phase and, in the process, the bit lines are at a different potential with respect to that of the two electrodes of the storage capacitor.