Memory using insulator traps
US6545314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.