Memory cell, memory cell arrangement and fabrication method

US6548861B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Herbert Palm · Hohenkirchen, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Jul 6, 2001
• Grant date: Apr 15, 2003
• Expiry date: Jul 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0413

Abstract

An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.