Non-volatile memory array using gate breakdown structures
US6549458B1 · kind B1 · utility
14Cited by
28References
23Claims
0Family size
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Key dates
| Filing date | Oct 25, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.