Fully integrated process for MIM capacitors using atomic layer deposition
US6551399B1 · kind B1 · utility
93Cited by
54References
12Claims
0Family size
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Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for fabricating a metal-insulator-metal capacitor by performing atomic layer deposition (ALD). A fully integrated process flow prevents electrode-dielectric contamination during an essential ex situ bottom electrode patterning step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.