Process for fabricating a self-aligned vertical bipolar transistor
US6551891B1 · kind B1 · utility
9Cited by
8References
22Claims
0Family size
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Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/051
Abstract
The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.