Process for device using partial SOI
US6551937B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 23, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.