Byte-wise tracking on write allocate
US6553473B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a write buffer. The write allocate logic allocates the cache line within the data cache, it stores data corresponding to the write miss within the allocated cache line, and queues a speculative write command directing an external bus to store said the data to the external memory in the event that transfer of the fill data is interrupted. The speculative write command is stored in the write buffer and, in the event of an interruption such as a bus snoop to the allocated cache line, the write buffer issues the speculative write command to the system bus, thereby writing the data to external memory. When the fill data is received from the system bus, it is filtered by byte-wise tracking logic such that only bytes positions which have not been written during the interim are updated in the allocated …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.