Process flow for capacitance enhancement in a DRAM trench

US6555430B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Michael P. Chudzik · Beacon, US
• Johnathan E. Faltermeier · San Jose, US
• Rajarao Jammy · Hopewell Junction, US
• Stephan Kudelka · Radeberg, DE
• Irene McStay · Hopewell Junction, US
• Kenneth T. Settlemyer, Jr. · Poughquag, US
• Helmut Tews · Poughkeepsie, US

Key dates

• Filing date: Nov 28, 2000
• Grant date: Apr 29, 2003
• Expiry date: Mar 7, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/964

Abstract

Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.