3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
US6556481B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | May 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.