Gate array with multiple dielectric properties and method for forming same

US6563183B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• William G. En · Sunnyvale, US
• Arvind Halliyal · Cupertino, US
• Minh-Ren Lin · Cupertino, US
• Minh Van Ngo · Fremont, US
• Cyrus E. Tabery · Sunnyvale, US
• Chih-Yuh Yang · San Jose, US

Key dates

• Filing date: Feb 28, 2002
• Grant date: May 13, 2003
• Expiry date: Feb 28, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant. The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant. The first dielectric constant and the second dielectric constant may be different and both may be greater than the dielectric constant of silicon dioxide.