Silicon-on-insulator vertical array device trench capacitor DRAM

US6566177B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Carl Radens · Lagrangeville, US
• Gary B. Bronner · Stormville, US
• Tze-Chiang Chen · Yorktown Heights, US
• Bijan Davari · Mahopac, US
• Jack A. Mandelman · Stormville, US
• Dan Moy · Bethel, US
• Devendra K. Sadana · Pleasantville, US
• Ghavam G. Shahidi · Pound Ridge, US
• Scott R. Stiffler · Hopewell Junction, US

Key dates

• Filing date: Oct 25, 1999
• Grant date: May 20, 2003
• Expiry date: Oct 25, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0387

Abstract

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isol…