Salicided gate for virtual ground arrays
US6566194B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.