Trench isolation processes using polysilicon-assisted fill
US6566228B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 26, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Feb 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.