Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US6566283B1 · kind B1 · utility
33Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76826
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.