Semiconductor array of floating gate memory cells and strap regions
US6566706B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.