Method of manufacturing semiconductor integrated circuit device having silicide layers
US6569742B1 · kind B1 · utility
69Cited by
3References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.