Dual metal gate CMOS devices and method for making the same
US6573134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.