Method of manufacturing an EEPROM device
US6576512B2 · kind B2 · utility
9Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2002 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Sep 23, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.