Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6577011B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Nov 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.