Formation of self-aligned buried strap connector
US6579759B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.