System and method for finding an operation/tool combination that causes integrated failure in a semiconductor fabrication facility
US6580960B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for finding operation/tool's combination which causes the integration failure in a semiconductor fabrication facility is disclosed. It comprises the steps of generating a candidate operation/tool list by selecting the operation/tool's that are more likely to cause said failure. Assign a weight value to each lot in the lot list for each operatioon/tool in said candidate operation/tool list, the weight value being a predetermined positive value for a bad lot, and a negative value for a good lot. Then select any pair of operation/tool's from said candidate operation/tool list and calculate a peak combination cumulative value for that pair of operation/tool's. Rank each pair of operation/tool's according to their corresponding peak combination cumulative values. It is determined the pair of operation/tool's with the greatest peak combination cumulative value the most likely to cause said failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.