Patent · US Expired

Semiconductor memory having a delay locked loop

US6584021B2 · kind B2 · utility

13Cited by

6References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Patrick Heyne · Hersbruck, DE
Thomas Hein · Hersbruck, DE
Torsten Partsch · San Jose, US
Marx Thilo · Villingen-Schwenningen, DE

Key dates

Filing date	Jan 15, 2002
Grant date	Jun 24, 2003
Priority date	—
Expiry date	Jan 15, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.