Self-testing of magneto-resistive memory arrays
US6584589B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2000 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.