Method for noise and power reduction for digital delay lines
US6586979B2 · kind B2 · utility
32Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.