Method and apparatus for implementing multiple memory buses on a memory module
US6587912B2 · kind B2 · utility
322Cited by
9References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.