Dual inlaid process using a bilayer resist
US6589711B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.