Sidewall spacer based fet alignment technology

US6593197B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Karsten Wieczorek · Dresden, DE
• Manfred Horstmann · Dresden, DE
• Rolf Stephan · Dresden, DE
• Michael Raab · Salem, DE

Key dates

• Filing date: Mar 19, 2001
• Grant date: Jul 15, 2003
• Expiry date: Apr 20, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.