Interconnect methodology employing a low dielectric constant etch stop layer
US6593632B1 · kind B1 · utility
14Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1999 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Nov 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.